What does $@ mean in a Makefile?

$@ is the file name of the target of the rule. In an explicit rule with multiple targets it is whichever target triggered the recipe. It is the most-used automatic variable, typically used as the output path in a compile command.

What is the difference between $^ and $+?

$^ is the list of all prerequisites with duplicates removed, while $+ keeps duplicates in their listed order. Use $+ only when repeated prerequisites are significant, such as repeated link libraries.

What is $* and when is it valid?

$* is the stem — the part of the target name matched by the % in a pattern rule. In an implicit rule like %.o: %.c, building foo.o sets $* to foo. In explicit rules $* is only set if the target ends in a recognised suffix.

How do $(@D) and $(@F) work?

Appending D gives the directory part and F gives the file-within-directory part of an automatic variable. For target src/foo.o, $(@D) is src and $(@F) is foo.o. They work on @, %, <, ?, ^, +, and *.

Does this tool need make installed?

No. It is a static, offline reference of GNU make's automatic and special variables. Nothing runs or is sent anywhere — searching happens entirely in your browser.

Makefile Special Variables Reference

Q: Does this tool need make installed?

No. It is a static, offline reference of GNU make's automatic and special variables. Nothing runs or is sent anywhere — searching happens entirely in your browser.

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GNU make automatic variables

When make runs a recipe it sets a handful of one-character automatic variables that name the target, the prerequisites and the pattern stem. Knowing them lets you write generic pattern rules instead of repeating file names. This reference lists every automatic variable, its meaning, and the D/F directory and file suffixes you can attach to each.

How it works

Automatic variables are set fresh for each rule that fires and are only valid inside that rule’s recipe (not in prerequisite lists, except via secondary expansion). The core ones:

%.o: %.c
	$(CC) -c $< -o $@        # $< = first prereq (foo.c), $@ = target (foo.o)

program: main.o util.o
	$(CC) $^ -o $@          # $^ = all prereqs deduped, $@ = program

For any automatic variable X, the forms $(XD) and $(XF) give the directory part and the file part. So with target build/foo.o, $(@D) is build and $(@F) is foo.o.

Tips and notes

$< is the first prerequisite — ideal as the single input to a compiler.
$^ deduplicates; reach for $+ only when repeats matter (link order).
$? is the subset of prerequisites that are newer than the target — handy for incremental archive updates.
$* (the stem) is the safe way to derive sibling file names in pattern rules.
These are case-sensitive single characters; $(MAKE), $(CURDIR) and friends are separate named special variables.