PCIe generations and bandwidth
PCI Express is the backbone that connects GPUs, NVMe SSDs, and add-in cards to the CPU. Each generation roughly doubles bandwidth, and links scale further by lane width. This reference lists every generation from PCIe 1.0 to 7.0 with its transfer rate, encoding scheme, and per-lane bandwidth, plus a calculator that multiplies any generation by any lane width.
How it works
PCIe quotes a raw signalling rate in gigatransfers per second (GT/s) per lane. To get usable bandwidth you remove line-encoding overhead. Generations 1 and 2 use 8b/10b encoding (20% overhead): PCIe 2.0 at 5 GT/s yields 500 MB/s per lane. Generations 3 through 5 use the far more efficient 128b/130b encoding (about 1.5% overhead): PCIe 3.0 at 8 GT/s yields about 985 MB/s per lane, and each later generation doubles that.
Total link bandwidth is per-lane bandwidth × lane width. Common widths are x1, x4 (most NVMe drives), x8, and x16 (most graphics cards). PCIe is full-duplex, so each lane carries that bandwidth simultaneously in both directions. Generations 6 and 7 switch from two-level NRZ to four-level PAM4 signalling, packing two bits per symbol, plus FLIT framing with forward error correction to keep errors in check.
Tips and notes
- A device negotiates to the lowest common generation and the narrowest common width, so a Gen5 SSD in a Gen3 slot runs at Gen3 speeds.
- Splitting lanes (bifurcation) lets one x16 slot host multiple devices, e.g. four x4 NVMe drives on a single x16 adapter, if the motherboard supports it.
- Higher generations have shorter clean signal reach, so PCIe 5.0 and beyond often need retimers or shorter, higher-quality traces and cables.
- The figures here are theoretical usable maximums; real throughput is also limited by the device controller, thermals, and the host’s available lanes.