Storage Interface Reference

SATA, NVMe, M.2, PCIe generations with throughput

Reference table of storage interface standards — SATA I/II/III, SAS, NVMe over PCIe 3.0/4.0/5.0, M.2, USB, and Thunderbolt — with maximum sequential transfer speeds, connectors, and notes.

Why is SATA III limited to about 600 MB/s?

SATA III runs at 6.0 Gbit/s but uses 8b/10b line encoding, so 20% is overhead. That leaves about 600 MB/s of usable bandwidth, and real drives top out near 550 MB/s.

Storage interface speeds at a glance

Storage drives connect over different buses, and each bus has a hard speed ceiling. This reference lists the common interfaces — from SATA hard-drive links to the latest PCIe 5.0 NVMe — with the maximum sequential transfer speed you can expect, plus the connector and a short note for each.

How it works

Every serial bus advertises a raw bit rate (for example SATA III at 6.0 Gbit/s), but the usable data rate is lower because of line encoding. SATA uses 8b/10b encoding, so every 10 transmitted bits carry 8 bits of data — a 20% tax that turns 6.0 Gbit/s into roughly 600 MB/s. PCIe 3.0 and newer use the far more efficient 128b/130b encoding, leaving only about 1.5% overhead, which is why PCIe scales so much better.

For PCIe, total bandwidth is per-lane rate × number of lanes. NVMe SSDs typically use an x4 link, so a PCIe 4.0 x4 drive gets four lanes of roughly 1.97 GB/s each, about 7.88 GB/s. Each PCIe generation doubles the per-lane rate, so the same x4 slot moves from ~3.94 GB/s (Gen3) to ~7.88 GB/s (Gen4) to ~15.76 GB/s (Gen5).

Tips and notes

  • M.2 is a slot shape, not a protocol — always check whether an M.2 drive is SATA or NVMe before assuming it is fast.
  • The B-key, M-key, and B+M-key notches on M.2 modules determine which slots accept them; NVMe drives are M-key.
  • External enclosures inherit the host port’s ceiling. A Gen4 NVMe stick in a USB 3.2 Gen 2 (10 Gbit/s) enclosure will run at roughly 1 GB/s, not 7 GB/s.
  • Sequential speed is only one dimension; random 4K IOPS often matters more for OS responsiveness and is not captured by these bus ceilings.